PROCESSOR 2

Families
Each type of processor has its own instruction set. Processors are grouped into the following families, according to their unique instruction sets:

-80 x 86 : the 'x' represents the family
-ARM
-IA-64
-MIPS
-Motorola 6800
-PowerPC
-SPARC

Pipelining

Pipelining is technology that improves instruction execution speed by putting the steps into parallel.
To understand the pipeline(TM)s mechanism, it is first necessary to understand the execution phases of an instruction. Execution phases of an instruction for a processor with a 5-step "classic" pipeline are as follows:

• FETCH: (retrieves the instruction from the cache;

• DECODE: decodes the instruction and looks for operands (register or immediate values);

• EXECUTE: performs the instruction (for example, if it is an ADD instruction, addition is performed, if it is a SUB instruction, subtraction is performed, etc.);

• MEMORY: accesses the memory, and writes data or retrieves data from it;

• WRITE BACK (retire): records the calculated value in a register.

-Instructions are organized into lines in the memory and are  loaded one after the other.
 
-instruction processing requires no more than the five preceding steps. Because the order of the steps is invariable (FETCH, DECODE, EXECUTE, MEMORY, WRITE BACK),
-The goal of the pipeline is to perform each step in parallel with the preceding and following steps, meaning reading an instruction (FETCH) while the previous step is being read (DECODE), while the step before that is being executed (EXECUTE), while the step before that is being written to the memory (MEMORY), and while the first step in the series is being recorded in a register (WRITE BACK). 



PIPELINE DATAPATH


A pipeline diagram shows the execution of a series of instructions.
—The instruction sequence is shown vertically, from top to bottom.
—Clock cycles are shown horizontally, from left to right.
—Each instruction is divided into its component stages. (We show five stages for every instruction, which will make the control unit easier.)
§This clearly indicates the overlapping of instructions. For example, there are three instructions active in the third cycle above.
—The “lw” instruction is in its Execute stage.
—Simultaneously, the “sub” is in its Instruction Decode stage.
—Also, the “and” instruction is just being fetched.



Single Cycle Datapath


DEFINITION
All instructions execute in a single cycle of the clock (positive edge to positive edge)

-Every step of the instruction is mapped onto the datapath from left to right. 

Pipeline Version of Datapath

-Register is needed between stages

  -Hold the information by the previous cycle.

-labeled as IF/ID because it separates the instruction fetch and instruction decode stages

IF / ID:

First and second pipe stages of an instruction

-the load needs  top register in stage 2
-As the processor doesnt know what instruction to be decoded,  it sign-extends the 16-bit constant and reads the registers into the ID/EX pipeline register.

EX: 
The third pipe stage of a load instruction

-The register is added to the sign-extended.
-EX/MEM pipeline register is used to place the sum. 

MEM and WB: 
The fourth and fifth pipe stages of a load instruction

-The address in the EX/MEM pipeline registers is used to read      the data memory.
 -Data is placed in the MEM/WB pipeline register. 
 -MEM/WB pipeline register is used to read the data and written into the register file.

EX: 
The third pipe stage of a store instruction

-EX/MEM pipeline register is used to load the second register to be used in the next stage.

MEM and WB: 
The fourth and fifth pipe stages of a store instruction.

-data memory is used to write  for the store. 
-When the data is written in memory,nothing is happening in stage 5 because there are no more things to do by the store instruction.

NUR AMIRA FARHANA BINTI ZAINOL
B031210351